The present invention relates to a clock circuit utilizing a clock delay and a method of designing the same.
For easy adjustment of the input/output timing, an increasing number of semiconductor integrated circuits (LSIs: hereinafter referred to as circuits) have adopted a synchronous design method in which signal transfer in a circuit is performed in synchronization with a clock signal.
Since the synchronous design method normally assumes simultaneous supply of a clock signal to each of synchronous devices, designing a circuit such that a maximum delay in signal processing (signal critical path delay) falls within a clock period ensures the operation of the entire circuit.
The arrival times of the clock signal at the individual synchronous devices, i.e., the difference between clock delay values are termed skew (clock skew). In the synchronous design method, it is required to design a clock circuit (portion of the circuit used to transmit and receive the clock signal) with zero skew.
As a representative of the synchronous design method, there has been proposed a method of designing a clock circuit wherein the number of devices and a wiring length are equal in each of clock signal supply paths extending from a clock source to the individual synchronous devices, such as one disclosed in U.S. Pat. No. 5,849,610 (Qing Zhu, xe2x80x9cMethod for Constructing a Planar Equal Path Length Clock Treexe2x80x9d, 1998).
It is to be noted that a signal delay is determined by a device delay DD and a wiring delay WD in a signal propagation path. With process variations during LSI fabrication or ambient variations such as voltage or temperature variations during LSI operation, the device delay DD undergoes a variation of xcex94DD per unit device and the wiring delay WD undergoes a variation of xcex94WD per unit wiring length.
Since the number of devices and the wiring length are equal in each of the clock signal supply paths in the aforementioned method of designing an equal path length clock circuit, the signal delay in each of the clock signal supply paths varies in the same manner so that the clock signal is supplied, while the skew is held minimum against the process variations, the temperature variations, or the like.
FIG. 25 shows variations in device delay, wiring delay, and signal delay resulting from temperature variations.
In FIG. 25, the graph plotted as the fine solid line represents variations in device delay (transistor delay) Dtr, the graph plotted as the fine broken line represents variations in wiring delay Dwr, the graph plotted as the thick solid line represents variations in first signal delay Dp1 in a first signal supply path in which the wiring delay is longer than the device delay, and the graph plotted as the thick broken line represents variations in second signal delay Dp2 in a second signal supply path in which the device delay is longer than the wiring delay. In FIG. 25, the horizontal axis represents temperature and the vertical axis represents delay time. Room temperature is designated at room (the dot-dash line in the drawing). A temperature lower than the room temperature and a temperature higher than the room temperature are designated at Tcool and Thot, respectively.
As shown in FIG. 25, if the proportion of device delay to wiring delay is different from one signal supply path to another, the variations in signal delay resulting from the variations in temperature are also different. By providing an equal proportion of device delay to wiring delay in each of the clock signal supply paths, i.e., by providing an equal number of devices and an equal wiring length in each of the clock signal supply paths, it is possible to provide an equal clock delay in each of the synchronous devices against the temperature variations.
However, with an increase in the number of devices integrated in an LSI and a relative increase in wiring resistance resulting from miniaturization, it has become extremely difficult to generate a clock circuit in which an equal number of devices and an equal wiring length is provided in each of clock signal supply paths. In other words, it has become difficult to design a clock circuit with zero clock skew. If clock skew is produced in the synchronous design method, the individual synchronous devices receive the signal at different times. As a result, part of signal transfer is not completed within a reception time so that the phenomenon of so-called mislatch (reception of a signal different from a target signal) occurs. Consequently, the circuit cannot perform correct signal transfer any more.
If a wire width larger than 0.5 xcexcm is used in semiconductor fabrication, the conventional synchronous design method, i.e., the zero skew clock design method can ignore the influence of a wiring resistance R on the clock delay, which allows the clock delay to be regarded as a time required by the driving device to supply charge equal to the wiring capacitance (including an input terminal capacitance at a signal reception point).
If a wire width smaller than 0.5 xcexcm is used in semiconductor fabrication, on the other hand, the influence of the wiring resistance R on the clock delay cannot be ignored any more. According to the approximation by Elmore (W. C. Elmore, xe2x80x9cThe Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiersxe2x80x9d, Journal of Applied Physics, Vol.19, 1948, pp.55-63), the wiring delay from a point P1 to a point P2 is proportional to the wiring resistance R1 from the point P1 to the point P2 and a total wiring capacitance (total wiring charge capacitance) C of the point P2 and its successors. Even if the circuit is designed such that each of the clock signal supply paths has an equal total wiring capacitance C0, clock delays (combination of R and C) in the individual synchronous devices are different depending on the configuration of branch lines, a wire width, or the like so that an increase in skew is unavoidable in the conventional zero skew clock design method.
As an example of a method of solving the foregoing problem caused by the introduction of miniaturization technology, while retaining the advantages of the conventional synchronous design method, Japanese Unexamined Patent Publication No. HEI 9-63291 (Yoda, Iida, Sasano, et al., xe2x80x9cclock Distributing Methodxe2x80x9d, 1997) discloses a method wherein logic design and clock circuit design are performed sequentially based on a zero skew clock circuit and then a skew value is calculated. Thereafter, a clock supply source is adjusted in accordance with a shortest delay in the synchronous devices to ensure the operation of the entire circuit. On the other hand, U.S. Pat. No. 5,896,299 (Arnold Ginetti et al., xe2x80x9cMethod and System for Fixing Hold Time Violations in Hierarchical Designsxe2x80x9d, 1999) proposes a method wherein logic design and clock circuit design are performed sequentially based on a zero skew clock circuit and then delay analysis is performed based on the result of the layout as the result of the design processes. Thereafter, a logic circuit is designed again by assuming that the clock skew from the clock source to each of the synchronous devices is Ts to ensure the operation of the entire circuit.
However, since each of the methods proposed by Japanese Unexamined Patent Publication No. HEI 9-63291 and U.S. Pat. No. 5,896,299 is based on the conventional zero skew clock circuit and aims at ensuring circuit operation by compensating the clock circuit or logic circuit, the foregoing problem caused by the introduction of miniaturization technology cannot be solved completely.
Besides the methods proposed by Japanese Unexamined Patent Publication No. HEI 9-63291 and U.S. Pat. No. 5,896,299, a semi-synchronous design method (Yoda, Sasaki, Takahashi, et al., xe2x80x9cClock Scheduling with Consideration of Modification Cost in Semi-Synchronous Circuitxe2x80x9d, Technical Report of Institute of Electronics, Information and Communication Engineers, CAS99-36, pp.45-52, 1999) has been proposed as a method of improving circuit performance, which is not based on a zero skew clock circuit. In accordance with the semi-synchronous design method, a clock circuit is designed by predetermining a clock delay value in each of the synchronous devices (skew scheduling) such that the number of devices and a wiring length in the clock circuit are minimized and circuit operation is ensured instead of targeting a zero skew clock circuit. The clock delay value in each of the synchronous devices is determined to satisfy the two inequalities given by the following expressions (1) and (2):
s(u)xe2x88x92s(v)+dmax(u, v)xe2x89xa6Txe2x80x83xe2x80x83(1)
0 less than dmin(u, v)+s(u)xe2x88x92s(v)xe2x80x83xe2x80x83(2).
In the expressions (1) and (2), s(u) and s(v) are respective clock delay values from a clock source to synchronous devices u and v, dmax(u, v) and dmin(u, v) are maximum and minimum values of the signal delay between the synchronous devices u and v (hereinafter referred to as a signal maximum delay value and a signal minimum delay value), and T is a circuit operation time (clock period). It is assumed that the signal propagates from the synchronous device u to the synchronous device v.
The expression (1) indicates that signal transfer between the synchronous devices u and v is performed correctly, i.e., the circuit operates normally if the clock period T is larger than the sum of the skew value between the 25 synchronous devices u and v and the signal maximum delay value dmax.
The expression (2) indicates that the circuit operates correctly if the skew value between the synchronous devices u and v is not so small as to cancel out the signal minimum delay value dmin.
The semi-synchronous design method provides a clock period T shorter than in a zero skew clock circuit, i.e., a circuit operation speed higher than in a zero skew clock circuit by realizing a clock circuit using clock delay values satisfying the expressions (1) and (2), i.e., by realizing a clock circuit which implements the result of skew scheduling.
In accordance with the semi-synchronous design method, a clock circuit which implements the result of skew scheduling can be realized easily by adjusting a wiring length or the like.
FIG. 26(a) shows an example of clock delay values in eight synchronous devices F1 to F8 obtained by skew scheduling. FIG. 26(b) shows an example of a clock circuit using the clock delay values shown in FIG. 26(a) for a two-dimensional layout arrangement of the synchronous devices F1 to F8. In FIG. 26(a), the vertical axis represents, by using the clock delay value in the synchronous device F1 as a standard (0), the clock delay values in the synchronous devices F1 to F8 as skew values from the standard.
As shown in FIG. 26(a), the synchronous devices F1 to F8 have the clock delay values within the range of 0 to 2000 pico-second (ps). As shown in FIG. 26(b), the clock circuit has redundant wiring inserted therein to implement the clock circuit using the clock delay values shown in FIG. 26(a).
In the semi-synchronous design method, a clock circuit which implements the result of skew scheduling can also be realized by adjusting the number of devices, i.e., a device delay instead of adjusting a wiring length, i.e., a wiring delay.
FIG. 27 shows an example of a clock circuit having buffers (driving devices) inserted therein such that the result of skew scheduling is implemented.
As shown in FIG. 27, the clock signal supply path between the clock input terminal and the synchronous device F1 is intervened by a first middle buffer MB1, a second middle buffer MB2, a third middle buffer MB3, and a first terminal buffer LB1. The clock signal supply path between the clock input terminal and the synchronous device F2 is intervened by the first middle buffer MB1, a fourth middle buffer MB4, and a second terminal buffer LB2. The clock signal supply path between the clock input terminal and the synchronous device F3 is intervened by the first middle buffer MB1 and a third terminal buffer LB3.
However, the semi-synchronous design method has encountered the problem that, as the miniaturization of an LSI advances, the determination of clock delay values satisfying the expressions (1) and (2), i.e., skew scheduling requires a longer time and the realization of a clock circuit which implements the result of skew scheduling becomes more difficult. Consequently, it becomes difficult to generate a clock circuit, while improving circuit performance including the operation speed of the circuit.
In the semi-synchronous design method, if the wiring length is adjusted to realize a clock circuit which implements the result of skew scheduling, a significant amount of redundant wiring is inserted in a clock circuit, as shown in FIG. 26(b), to disadvantageously increase power consumption or layout area. Similar problems also occur when a clock circuit which implements the result of skew scheduling is realized by adjusting the number of devices. If the total wiring length of the clock circuit increases, an increasing number of wires are brought closer and adjacent to each other, which leads to the problem that the influence of crosstalk (wire-to-wire interference resulting from a change in signal voltage) is likely to increase.
Since the semi-synchronous design method adjusts the wiring length or the number of devices without considering variations in clock delay values resulting from process variations, temperature variations, or the like, the proportion of device delay to wiring delay is different in the different clock signal supply paths from the clock source to the individual synchronous devices. This causes the problem that delay variations (variations in the respective clock delay values of the synchronous devices), i.e., skew errors resulting from process variations, temperature variations, or the like are increased.
In view of the foregoing, it is therefore an object of the present invention to effect efficient skew scheduling and ensures the realization of a clock circuit which implements the result of skew scheduling. It is another object of the present invention to provide a clock circuit capable of improving circuit performance, inhibiting power consumption or layout area from being increased, and suppressing skew errors resulting from process variations, temperature variations, or the like.
To attain the objects, a first method of designing a clock circuit according to the present invention is based on a method of designing a clock circuit for supplying a clock signal to each of a plurality of synchronous devices in an integrated circuit and comprises: a discrete clock determining step of determining a group of discrete clock delay values composed of a finite number of discrete values to be allocated as respective clock delay values to the plurality of synchronous devices based on an arrangement of the synchronous devices or on timing constraints; a clock allocating step of allocating, as a selected clock delay value, the clock delay value selected from the group of discrete clock delay values to each of the plurality of synchronous devices, while ensuring an operation of the integrated circuit; and a clock circuit designing step of designing the clock circuit for supplying the clock signal to each of the plurality of synchronous devices in accordance with the selected clock delay value.
In accordance with the first method of designing a clock circuit, the group of discrete clock delay values composed of a finite number of discrete values is determined and then a selected clock delay value selected from the group of discrete clock delay values is allocated to each of the synchronous devices. Thereafter, a clock circuit for supplying a clock signal to each of the synchronous devices in accordance with the selected clock delay value is designed. Since the clock delay value to be allocated to each of the synchronous devices is selected from the group of discrete clock delay values, the range in which the selected clock delay values are searched for is limited so that efficient skew scheduling is performed. Since the selected clock delay values allocated to the respective synchronous devices are limited, a clock circuit which implements the result of skew scheduling can be generated positively by adjusting, e.g., the number of devices, the wiring length, or the like.
In the first method of designing a clock circuit, the group of discrete clock delay values is preferably composed of integral multiples of a basic clock delay unit time determined based on the arrangement of the plurality of synchronous devices or on the timing constraints.
This allows easy determination of the group of discrete clock delay values.
If the group of discrete clock delay values is composed of integral multiples of the basic clock delay unit time, the basic clock delay unit time is a signal delay value produced when a driving device used in the clock circuit drives a specified capacitance and the specified capacitance is preferably determined based on a total charge capacitance which is a total sum of a wiring capacitance when the plurality of synchronous devices are connected to each other with a shortest wiring length based on the arrangement of the synchronous devices and respective input terminal capacitances of the synchronous devices or on the timing constraints.
This allows easy determination of the basic clock delay unit time.
In the first method of designing a clock circuit, the discrete clock determining step preferably includes the step of: calculating maximum and minimum values of implementable clock delay values as a maximum clock delay value and a minimum clock delay value based on the number of driving devices used in the clock circuit or on an area of the integrated circuit and determining the group of discrete clock delay values within a range from the minimum clock delay value to the maximum clock delay value.
This further limits the range in which the clock delay value to be allocated to each of the synchronous devices is searched for and allows more efficient skew scheduling. Since the selected clock delay values allocated to the synchronous devices are further limited, the clock circuit which implements the result of skew scheduling can be generated more positively by adjusting, e.g., the number of devices, the wiring length, or the like.
Preferably, the first method of designing a clock circuit further comprises, prior to the discrete clock determining step, the step of: calculating a shortest operation period for the integrated circuit, wherein the discrete clock determining step preferably includes the step of: calculating maximum and minimum values of the clock delay values which can implement the shortest operation period as a maximum clock delay value and a minimum clock delay value and determining the group of discrete clock delay values within a range from the minimum clock delay value to the maximum clock delay value.
This further limits the range in which the clock delay value to be allocated to each of the synchronous devices is searched for and allows more efficient skew scheduling. Since the selected clock delay value of each of the synchronous devices is further limited, the clock circuit which implements the result of skew scheduling can be generated more positively by adjusting, e.g., the number of devices or the wiring length. Since the selected clock delay value of each of the synchronous devices is limited to the range in which the shortest operation period of the integrated circuit, i.e., the system limit operation period is implementable, it becomes possible to bring the clock period to a value in the vicinity of the system limit operation period and thereby improve the performance of the circuit (LSI).
Preferably, the first method of designing a clock circuit further comprises, prior to the clock allocating step, the step of: determining a clock delay objective value which is an objective value of the clock delay value to be allocated to each of the plurality of synchronous devices, wherein the clock allocating step preferably includes the step of: minimizing an evaluation function value determined based on a difference between the clock delay value selected from the group of discrete clock delay values and allocated to each of the synchronous devices and the clock delay objective value and on an operation time of the integrated circuit.
This brings the clock delay value of each of the synchronous devices closer to the clock delay objective value, reduces the operation time of the integrated circuit, and thereby improves the performance of the integrated circuit.
If the first method comprises the step of determining the clock delay objective value, the clock delay objective value is preferably a constant common to each of the plurality of synchronous devices.
By thus using the clock delay value (constant common to each of the synchronous devices) of each of the synchronous devices that has been obtained in accordance with, e.g., a zero skew clock design method as the clock delay objective value of each of the synchronous devices, it is possible to improve the performance of the integrated circuit by only performing a reduced number of correction steps with respect to the zero skew clock circuit.
Preferably, the first method of designing a clock circuit further comprises, prior to the clock allocating step, the step of: determining, for each of the plurality of synchronous devices, the synchronous device adjacent thereto based on the arrangement of the synchronous devices, wherein the clock allocating step preferably includes the step of: minimizing an evaluation function value determined based on a difference between the clock delay value selected from the group of discrete clock delay values and allocated to each of the plurality of synchronous devices and the clock delay value selected from the group of discrete clock delay values and allocated to the adjacent synchronous device thereof and on an operation time of the integrated circuit.
This adjusts the respective clock delay values of the adjacent synchronous devices to equal or nearly equal values, reduces the operation time of the integrated circuit, and thereby improves the performance of the integrated circuit. If the clock delay values of the adjacent synchronous devices are adjusted to equal or nearly equal values, the synchronous devices can be connected to each other with a short wire so that the wiring length of the clock circuit is reduced and power consumption and layout area are also reduced.
Preferably, the first method of designing a clock circuit further comprises, prior to the clock allocating step, the step of: determining, for each of the plurality of synchronous devices, the synchronous device adjacent thereto based on the arrangement of the synchronous devices, wherein the clock allocating step preferably includes the step of: minimizing an evaluation function value determined based on a ratio of a difference between the clock delay value selected from the group of discrete clock delay values and allocated to each of the plurality of synchronous devices and the clock delay value selected from the group of discrete clock delay values and allocated to the adjacent synchronous device thereof to a distance between each of the synchronous devices and the adjacent synchronous device thereof and on an operation time of the integrated circuit.
This adjusts the respective clock delay values of those of the adjacent synchronous devices disposed at a relatively small distance to equal or nearly equal values, reduces the operation time of the integrated circuit, and thereby improves the performance of the integrated circuit. If the clock delay values of those of the adjacent synchronous devices disposed at a relatively small distance are adjusted to equal or nearly equal values, the synchronous devices can be connected to each other with a shorter wire so that the wiring length of the clock circuit is further reduced and power consumption and layout area are also further reduced.
Preferably, the first method of designing a clock circuit further comprises, prior to the clock allocating step, the step of: determining, for each of the plurality of synchronous devices, the synchronous device adjacent thereto based on the arrangement of the synchronous devices and determining a power source line connected to each of the synchronous devices based on power source line data, wherein the clock allocating step preferably includes the step of: minimizing an evaluation function value determined based on an operation time of the integrated circuit and on a function value which assumes a specified value other than zero at the time when the power source line connected to each of the plurality of synchronous devices is coincident with the power source line connected to the adjacent synchronous device thereof and the clock delay value selected from the group of discrete clock delay values and allocated to each of the synchronous devices is the same as the clock delay value selected from the group of discrete clock delay values and allocated to the adjacent synchronous device thereof and assumes zero at all other times.
This reduces the operation time of the integrated circuit and thereby improves the performance of the integrated circuit, while preventing a situation where clock delay values equal or nearly equal to each other are allocated to the synchronous devices connected to the same power source line and adjacent to each other. If such a situation is prevented, the synchronous devices connected to the same power source line and adjacent to each other are prevented from operating simultaneously, so that a local increase in the amount of consumed current is suppressed.
If the first method comprises the step of determining the adjacent synchronous device and the power source line to be connected, the adjacent synchronous device is preferably determined among those of the plurality -of synchronous devices which are positioned at a specified distance or farther away from a basic power source line based on the power source line data.
This eases constraints during skew scheduling and thereby allows easy skew scheduling.
In the first method of designing a clock circuit, the clock circuit designing step preferably includes: a cluster forming step of forming at least one or more clusters each composed of those of the plurality of synchronous devices to which the same selected clock delay value has been allocated in the clock allocating step such that a signal delay value when the synchronous devices contained in each of the clusters are connected to each other with a minimum wiring length based on the arrangement of the synchronous devices and when the cluster is driven by one driving device is not more than a discrete clock delay value difference which is a difference between one of the selected clock delay values corresponding to the cluster and the other of the selected clock delay values smaller than and closest to the one of the selected clock delay values; and a driving device placing step of placing one driving device in each of the clusters and determining a wiring connection between an output terminal of the driving device and an input terminal of each of the synchronous devices contained in the cluster in which the driving device has been placed such that a signal delay value when the cluster is driven by the driving device is equal to the discrete clock delay value difference.
By thus connecting the individual driving devices, a clock circuit which implements the result of skew scheduling can be generated positively.
If the clock circuit designing step includes the cluster forming step and the driving device placing step, the cluster forming step preferably includes the step of: determining the number of clusters to be formed by using a total sum of a wiring capacitance when the synchronous devices to which the same selected clock delay value has been allocated are connected to each other with a minimum wiring length based on the arrangement of the plurality of synchronous devices and respective input terminal capacitances of the synchronous devices to which the same selected clock delay value has been allocated.
This ensures the adjustment of a signal delay value when the synchronous devices contained in each of the clusters are connected with a minimum wiring length and when each of the clusters is driven by one driving device to a value not more than the discrete clock delay value difference.
If the clock circuit designing step includes the cluster forming step and the driving device placing step, the driving device placing step preferably includes the step of: placing the same type of driving devices in the individual clusters.
This allows the step of determining the number of clusters to be performed easily and thereby allows the clusters to be generated easily.
If the clock circuit designing step includes the cluster forming step and the driving device placing step, the clock circuit designing step preferably further includes, after the driving device placing step, the step of: adjusting a location of the driving device such that the driving device is closer to, of the synchronous devices to which the other of the selected clock delay values has been allocated, that one closest to the driving device.
This achieves a reduction in redundant wiring in each of the clusters.
If the clock circuit designing step includes the cluster forming step and the driving device placing step, the clock circuit designing step preferably further includes, between the cluster forming step and the driving device placing step: a cluster changing step of reallocating, if an operation of the integrated circuit is ensured, the selected clock delay value corresponding to the one of the clusters formed in the cluster forming step to the synchronous device to which the selected clock delay value smaller than the selected clock delay value corresponding to the one of the clusters has been allocated and inserting, in the one of the clusters, the synchronous device to which the selected clock delay value has been reallocated.
By thus additionally inserting the synchronous device, the cluster delay value in one of the clusters (a signal delay value when one of the clusters is driven by one driving device) can be brought closer to the discrete clock delay value difference so that redundant wiring in one of the clusters is reduced and power consumption and layout area are also reduced thereby. Since the number of synchronous devices contained in each of the clusters is increased, the total number of clusters, i.e., the total number of driving devices placed in the respective clusters is reduced so that power consumption and layout area are further reduced.
If the clock circuit designing step includes the cluster changing step, the cluster changing step preferably includes the step of: reallocating the selected clock delay value corresponding to the one of the clusters to, of the plurality of synchronous devices, that one which is located adjacent the synchronous device contained in the one of the clusters and to which the smaller selected clock delay value has been allocated.
This reduces the wiring length of the clock circuit and thereby suppresses increased power consumption and increased layout area.
If the clock circuit designing step includes the cluster changing step, the clock circuit designing step preferably includes, between the cluster changing step and the driving device placing step, the step of: allocating the clock delay value selected from the group of discrete clock delay values to the unclustered one of the synchronous devices to which the smaller selected clock delay value has been allocated, while ensuring the operation of the integrated circuit.
This allows the selected clock delay value allocated to the unclustered synchronous device to be improved by using a specified evaluation function value and allows easier clustering of the synchronous devices.
If the clock circuit designing step includes the cluster forming step and the driving device placing step, the first method further comprises, after the clock circuit designing step: a cluster changing step of reallocating, if an operation of the integrated circuit is ensured, the selected clock delay value corresponding to one of the clusters formed in the cluster forming step to the synchronous device contained in another of the clusters formed in the cluster forming step and inserting, in the one of the clusters, the synchronous device to which the selected clock delay value has been reallocated.
By thus moving the locations of the synchronous devices between the clusters, the cluster delay value of each of the clusters can be brought closer to the discrete clock delay value difference so that redundant wiring in each of the clusters is reduced and power consumption and layout area are also reduced. In the case where all the synchronous devices contained in the other of the clusters can be inserted in the one of the clusters, the total number of clusters, i.e., the total number of driving devices placed in the respective clusters is reduced so that power consumption and layout area are further reduced.
If the clock circuit designing step includes the cluster forming step and the driving device placing step, the first method preferably further comprises, after the clock circuit designing step: a clock reallocating step of reallocating, to each of the clusters, a continuous clock delay value which is one of continuous values from a cluster minimum clock delay value to a cluster maximum clock delay value by using, as the cluster minimum clock delay value, the clock delay value when the wiring connection within each of the clusters is achieved with the cluster minimum wiring length and using, as the cluster maximum clock delay value, the selected clock delay value corresponding to each of the clusters so as to implement an actualized circuit operation time which is an operation time of the integrated circuit implemented when the clock signal is supplied to each of the plurality of synchronous devices in accordance with the selected clock delay value and redetermining the wiring connection within each of the clusters such that the clock signal is supplied to the synchronous device contained in each of the clusters in accordance with the continues clock delay value reallocated to each of the clusters.
In the arrangement, the wiring connection within each of the clusters is achieved with a minimum wiring length except for the case where the actualized circuit operation time is not implemented. By thus reducing unnecessary redundant wiring, increased power consumption and increased layout area resulting from clock wiring can be prevented.
If the first method comprises the clock reallocating step, the clock reallocating step is preferably performed once with respect to each of the clusters in decreasing order of the selected clock delay values corresponding to the respective clusters.
This allows easy reallocation of the continuous clock delay value to each of the clusters.
If the first method comprises the clock reallocating step, the clock reallocating step preferably includes the step of: setting the selected clock delay value corresponding to each of the clusters as an initial value of the cluster maximum clock delay value and renewing the cluster maximum delay value with the continuous clock delay value reallocated to each of the clusters, the step being performed at least once with respect to each of the clusters till the cluster maximum clock delay value is no more renewed with a new value.
This further reduces the continuous clock delay value reallocated to each of the clusters and further reduces unnecessary redundant wiring.
If the clock circuit designing step includes the cluster forming step and the driving device placing step, the first method preferably further comprises, after the clock circuit designing step: a clock reallocating step of reallocating, to each of the clusters, a continuous clock delay value which is one of continuous values from a cluster minimum clock delay value to a cluster maximum clock delay value by using, as the cluster minimum clock delay value, the clock delay value when the wiring connection within each of the clusters is achieved with the minimum wiring length and using, as the cluster maximum clock delay value, the selected clock delay value corresponding to each of the clusters so as to minimize an operation time of the integrated circuit and redetermining the wiring connection within each of the clusters such that the clock signal is supplied to the synchronous device contained in each of the clusters in accordance with the continuous clock delay value reallocated to each of the clusters.
This adjusts the operation time of the integrated circuit shorter than the actualized circuit operation time and closer to the system limit operation period, so that the performance of the circuit (LSI) is improved.
A second method of designing a clock circuit according to the present invention is based on a method of designing a clock circuit for supplying a clock signal to each of a plurality of synchronous devices in an integrated circuit and comprises: a first step of determining, for a non-inverting operation synchronous device which operates on a rising edge of the clock signal, a first operation response time between inputting of the clock signal and the operation of the non-inverting operation synchronous device and determining, for an inverting operation synchronous device which operates on a falling edge of the clock signal, a second operation response time between the inputting of the clock signal and the operation of the inverting operation synchronous device; and a second step of allocating, as a clock delay value, either of the first and second operation response times to each of the plurality of synchronous devices, while ensuring an operation of the integrated circuit, and replacing that one of the plurality of synchronous devices to which the first operation response time has been allocated as the clock delay value with the non-inverting operation synchronous device, while replacing that one of the plurality of synchronous devices to which the second operation response time has been allocated as the clock delay value with the inverting operation synchronous device.
In accordance with the second method of designing a clock circuit, the first operation response time is determined for the non-inverting operation synchronous device and the second operation response time is determined for the inverting operation synchronous device. Then, either of the first and second operation response times is allocated as the clock delay value to each of the synchronous devices. Thereafter, the synchronous device to which the first operation response time has been allocated is replaced with the non-inverting operation synchronous device and the synchronous device to which the second operation response time has been allocated is replaced with the inverting operation synchronous device. Since the clock delay value to be allocated to each of the synchronous devices is selected from the first and second operation response times, the range in which the clock delay value is searched for is limited so that efficient skew scheduling is performed. Since the clock circuit is generated by replacing the synchronous device to which the first or second operation response time has been allocated with the non-inverting or inverting operation synchronous device, a clock circuit which implements the result of skew scheduling can be generated positively without adjusting a delay in the driving device, a wiring capacitance, or the like, i.e., without changing the wiring connection in the clock circuit or the like. The performance of the circuit can be improved easily by changing the setting of the first or second operation response time.
A clock circuit according to the present invention is based on a clock circuit for supplying a clock signal to each of a plurality of synchronous devices in an integrated circuit, wherein the clock signal is supplied to each of the plurality of synchronous devices in accordance with a selected clock delay value which is a clock delay value allocated to each of the synchronous devices, while an operation of the integrated circuit is ensured, the selected clock delay value being selected from a group of discrete clock delay values composed of a finite number of discrete values to be allocated as the respective clock delay values to the plurality of synchronous devices.
In the clock circuit according to the present invention, the clock signal is supplied to each of the synchronous devices in accordance with the selected clock delay value selected from the group of discrete clock delay values and allocated to each of the synchronous devices. This limits the range in which the clock delay value to be allocated to the synchronous device is searched for so that efficient skew scheduling is performed. Since the clock delay value to be allocated to each of the synchronous devices is limited, a clock circuit which implements the result of skew scheduling can be generated positively by adjusting, e.g., the number of devices or the wiring length.
In the clock circuit according to the present invention, at least one or more clusters are preferably formed from the plurality of the synchronous devices, each of the clusters being composed of the synchronous devices to which the same selected clock delay value has been allocated, one driving device is preferably placed in each of the clusters, and a wiring connection between an output terminal of the driving device and an input terminal of each of the synchronous devices contained in the cluster in which the driving device has been placed is preferably determined such that a signal delay value when the cluster is driven by the driving device is equal to a discrete clock delay value difference which is a difference between one of the selected clock delay values corresponding to the cluster and the other of the selected clock delay values smaller than and closest to the one of the selected clock delay values.
By thus connecting the individual driving devices, a clock circuit which implements the result of skew scheduling can be generated positively.
In this case, the same type of driving devices are preferably placed in the individual clusters.
This allows easy formation of the clusters.
In the clock circuit according to the present invention, the clock circuit is preferably composed of a plurality of driving devices of the same type and a total charge capacitance which is a total sum of respective wiring capacitances and respective input terminal capacitances of the synchronous devices driven by each of the plurality of driving devices is preferably adjusted to an equal specified value within a 20% error.
This reduces variations in signal delay produced in the individual stages of each of the clock signal supply paths for supplying a clock signal from the clock source to each of the synchronous devices so that skew errors resulting from process variations, temperature variations, or the like are suppressed.
In the clock circuit according to the present invention, the clock circuit preferably has a plurality of clock signal supply path for supplying the clock signal from a clock source to each of the plurality of synchronous devices and a ratio between an amount of wiring delay and an amount of transistor delay in each of the plurality of clock signal supply paths is preferably adjusted to an equal specified value within a 20% error based on an arrangement of the plurality of synchronous devices or on timing constraints.
Since the ratio between the amount of wiring delay and the among of transistor delay in each of the clock signal supply paths has thus been adjusted to a nearly equal specified value, the clock delays when the clock signal is supplied to each of the synchronous devices change in association in response to a temperature change so that circuit operation is compensated over a wide temperature range.
In this case, the equal specified value is preferably a ratio between an amount of wiring delay and an amount of transistor delay in a critical path of the integrated circuit.
Since the ratio between the amount of wiring delay and the amount of transistor delay in each of the clock signal supply paths has thus been adjusted to a value nearly equal to the ratio between the amount of transistor delay and the amount of wiring delay in the critical path, the clock delays when the clock signal is supplied to each of the synchronous devices change in association with the signal delay in the critical path in response to a temperature change so that circuit operation is compensated positively over a wide temperature range.